Research

PhD defence by Dipen Narendra Dalal

Time

22.11.2021 kl. 13.00 - 16.00

Description

Dipen Narendra Dalal, AAU Energy, will defend the thesis "Demonstration of 10 kV Silicon Carbide Power Semiconductor Technology in Medium Voltage Power Conversion"

TITLE

Demonstration of 10 kV Silicon Carbide Power Semiconductor Technology in Medium Voltage Power Conversion

PHD DEFENDANT

Dipen Narendra Dalal

SUPERVISOR

Professor Stig Munk-Nielsen

CO-SUPERVISOR

Associate Professor Christian Uhrenfeldt, Associate Professor ‪Szymon Bęczkowski, Associate Professor Michael Møller Bech

MODERATOR

Associate Professor Amir Sajjad Bahman

OPPONENTS

Associate Professor Pooya Davari, Aalborg University, Denmark (Chairman)
Professor Hans-Peter Nee, KTH Royal Institute of Technology 
Associate Professor Dimosthenis Peftisis, Norwegian University of Science and Technology

 

ABSTRACT

In present-day electricity networks, power electronics is widely employed or one
can say “omnipresent” as an enabling technology for the conversion and control
of electric power at generation, transmission, distribution and consumer end.
At the consumer end, industrial sector constitutes the single largest share in
the global electric energy consumption. A significant portion of electric energy
in the industrial sector is consumed by medium voltage motor drive systems,
that often utilize high power (375 kW – 10,000 kW), medium voltage (1 kV –
10 kV) power electronic converters. At the distribution end, high power medium
voltage converters are used for grid support functionalities. At generation end,
penetration of renewable energy sources such as photovoltaics and wind with
their increasing power generation capabilities, demand for medium voltage
power electronics which can offer potential benefits in terms of system level
efficiency gains and reduced levelized cost of energy production.
Power semiconductor devices constitute the key building block of modern
power electronic converters. Commercial high power medium voltage converters
utilize Silicon (Si) based power semiconductor devices, which has evolved as a
mature technology and dominated power electronics industry for the past years.
With Si based power semiconductor devices reaching their theoretical limits of
performance, newly emerging Silicon Carbide (SiC) based wide band gap (WBG)
devices are foreseen as a likely alternative to Si based devices. The SiC based
power semiconductor devices, with their smaller size, high blocking voltage
capability, faster switching speed and high temperature withstand capability
offer significant benefits to power electronic converters in terms of simplification
of power converter topology with increased efficiency and power density.
This PhD thesis demonstrates 10 kV SiC power semiconductor devices in
medium voltage power conversion applications. The high rate of change of
voltage (dv/dt) in case of SiC Metal Oxide Field Effect Transistor (MOSFET)
due to the medium voltage levels and fast switching transient requires careful
consideration of electrical parasitics. Especially parasitic capacitive couplings
to limit the displacement currents during the switching transients that can
adversely impact electromagnetic interference and compatibility as well as
switching performance for the power electronic converter. In particular, parasitic
v
capacitive couplings within the power modules, as well as external interfacing
circuits such as gate drivers and passive components. The PhD thesis begins
with introducing state of the art and 10 kV half-bridge SiC MOSFET power
modules utilised in this research work. Thereafter, a gate driver with high
voltage isolation and a very low coupling capacitance (< 3 pF) is presented.
The main contribution of the PhD thesis lays in investigating the power module
parasitic capacitance induced displacement current path and its impact on the
switching energy dissipation. By solving scientific challenges and implementing
mitigation techniques, to lessen the impact of high dv/dt induced displacement
currents on the half-bridge power module and circuits interfacing power modules,
a 50 kVA, 4.16 kV rated medium voltage power stack demonstrator is designed,
built and experimentally validated close to its intended operating condition. For
designed medium voltage power stack, efficiency higher than 99% is inferred from
the converter measurements in a DC fed three phase back-to-back regenerative
test setup. The PhD thesis concludes by summarizing the research and the
contemplated future work.

 

THE DEFENCE will be IN ENGLISH - all are welcome.

 

 

Host

AAU Energy

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